Principal Engineer-Software Configurator Engineer

Microchip Armenia CJSC

- Read and understand the Silicon Architecture specifications - Define macros/primitves and guide and/or develop the software core to configure IP blocks in Microchip FPGAs like - SERDES, Etherent, PCIe, PLL and Memories (DDR, RAMs and uPROM) involving tcl based core development, UI development and Netlist generation - A tcl based core development to generate Verilog net list to connect various macros/primitves. Few complex cores - will involve UI development using C++ and Qt frameworks - Generation of design files (netlist, register settings, timing constraints files) for various hard IP blocks in Microchip FPGAs - Should be able to capture the requirements and create Software requirements document - Should be able to create simple designs to test the Synthesis & PnR flow for generated netlist - Should be able to estimate the efforts and provide the plan for completing the requirements - Propose / review test plans - Work across with multiple teams in accomplishing the tasks - Assist and train Junior engineers - Debugging and Bug fixing

- Bachelors or Masters in Electronics Engineering - 8+ years of experience in EDA software core development - Experience with industrial standard protocols like PCIe, High speed Serial Connectivity Ethernet, SPI, I2C, USB, GPIO, AXI/AHB and Memory architectures DDR/SDRAM/DMA - Exposure to FPGAs and FPGA software tool chain - Experience in writing scripts in Tcl/Perl/Python - Experience in Verilog, Developing GUI using Qt is plus - Excellent communication and problem-solving skills are must - Experience in software development using C++ Programming Language is plus - Good verbal & written communication - Good attitude, result driven & ability to deliver on next gen technology

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