Principal Engineer- FPGA HDL Simulation Model Development
Company
Microchip Armenia CJSC
Category
Job Address
Application Deadline
IT
Yerevan, Armenia
05/07/2025
Responsibilities
- Develop behavioural HDL models for various FPGA functional blocks like basic logic cells, RAM, PLL, SerDes, PCIe, \ DDR, Ethernet, AMBA Target & Initiators etc
- Focus on developing cycle accurate and fast HDL simulation models by using Verilog/System Verilog HDL
- Develope Verilated and SystemC based simulation models.- Debug on customer issues, bug-fixing, and maintenance of simulation models
- Analyse the simulation models and make implementation choices to optimize the simulation run time, memory utilization etc
- Simulation library generation and qualification through regressions
- Perform pre-synthesis, post-synthesis, and Back Annotated (BA) simulation
- Work with other teams to get BA simulation data (sdf) and add it in simulation model
- Read and understand the Silicon Architecture specifications
- Should be able to estimate the efforts and provide the plan for completing the requirements
- Propose / review test plans and reports
- Assist and train Junior engineers in the team
Required Qualifications
- Bachelors or Masters in Electronics Engineering
- 8+ years of experience in EDA software development
- Discipline (BE/BTech/ME/MTech preferred) and 8+ years of experience in FPGA and HDL development
- Experience in FPGA HDL design with Verilog/System Verilog
- Expereience in Verilated, SystemC simulation is plus
- Experience using industry standard HDL simulation tools (e.g. VCS/VCSMX, MODELSIM/QUESTASIM, NCSIM/XCELIUM, or ALDEC Riviera)
- Should be familiar with FPGA architecture and AMBA bus protocols.
- Experience using scripting languages (e.g., Python, TCL, PERL, BASH) is preferred
- Experience on SystemC, DPI, PLI, Renode is plus
- Excellent communication and problem-solving skills are a must.
- Good attitude, result driven & ability to deliver on next gen technology
Application Procedures